Job Description
Have you taken a career break and had your resume rejected because of your resume gap? Intel is offering 16-week paid returnships for experienced professionals ready to return to the workforce. If you have taken a break of at least one year for the following reasons we welcome you to apply:
Starting or raising a family
Military service/military spouse
Community service/volunteer work
Caring for a family member
Teaching
Now is an exciting time for Intel’s Design Enablement Group! This position is within the Design Enablement (DE) organization of Technology Development (TD). At Intel, Design Enablement is one of the key pillars enabling Intel to deliver winning products in the marketplace. Your work will directly enable design teams to get to market faster with leadership products on cutting edge technologies and partner with Technology Development to deliver cost-effective, competitive design platform.
In this position you will help us with the following responsibilities:
Develop, design, and test analog, high-speed I/O, and memory circuits in Intel’s leading-edge technology nodes and optimize power/performance/area (PPA) to provide feedback that drives design-technology co-optimization for Intel process technologies.
Work with suppliers of CAD tools for custom design, layout, and design signoff to enable and validate features supporting the requirements of leading-edge process technologies.
Develop and validate technology files and other collaterals used by industry standard custom design, layout, and signoff CAD tools, including PCells/PyCells.
Develop automation software and scripts for generation and validation of Process Design Kit (PDK) collaterals and analysis of CAD tool results.
Develop automation to generate schematics, layouts, and library collaterals.
Develop and evaluate analog / mixed signal components for use with test equipment and other hardware systems.
Conduct or participate in multidisciplinary research and collaborate with design, layout and/or hardware engineers in the design, development, and utilization of productivity enhancement layout tools and design rule checkers, electronic data processing systems software.
Determines computer user needs, advises hardware designers on machine characteristics that affect software systems such as storage capacity, processing speed, and input/output requirements, designs and develops compilers and assemblers, utility programs, and operating systems.
Work closely with runset developers and rule writers on validating the rules.
Work with EDA on tool developments/improvements to enhance performance, add functionality and improve capacity.
Validate Process Design Kit (PDK)
Working with multiple EDA companies to co-develop extraction solutions that will be used both internally and as part of Intel's foundry program.
Analyzing and testing programs and products before formal launch
Troubleshooting coding problems quickly and efficiently to ensure a productive workplace
Software Engineer
In this position you will help us with one or more of the following responsibilities:
Behavioral traits that we are looking for:
Written and verbal communication skills
Teamwork, problem-solving, and data analysis
Ability to work across geographical locations
These positions are not eligible for Immigration Sponsorship.
These roles can be done remotely.
Qualifications
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications
Candidates must have been out of the paid workforce for at least one year.
You should have Bachelor’s degree OR Master's degree OR PhD in Electrical Engineering, Computer Engineering, Computer Science, or other related Electrical Scientific STEM field, with 3+ years of work experience in one or more of the following areas:
Design of CMOS analog/mixed-signal, custom digital, memories, data converters, RF, or high-speed circuits.
Layout of analog, RF, or digital circuits on advanced process technology nodes.
Programming or scripting in Python, Perl, Tcl, SKILL, C++, or Unix shell.
Circuit design: VLSL, circuit simulation
Design automation: ASIC Design, Place and Route, Virtuoso
Physical design: cadence virtuoso, layout automation, physical verification, parasitics, runsets
Semiconductor physics, devices modeling
Electromagnetic simulation
Programming languages: python/skill/Perl/ruby
Solving problems using efficient computer algorithm and programming techniques.
Software development/programming in Python languages
Object oriented programming, data structures, algorithms, and database.
Solving problems using efficient computer algorithm and programming techniques.
Software development/programming in Python languages
Object oriented programming, data structures, algorithms, and database.
Circuit design and VLSI technology
Computer architecture, RTL, Verilog, System Verilog, exposure to OVM UVM
Knowledge of Chip floor planning, layout integration, layout design rules and schematic/layout comparison debug and validation
Experience with floor planning, layout design, and verification CAD tools
Digital system RTL based design, including DFT, system architecture, and integration of various IPs into subsystems
Digital, mixed-signal, memory, and/or analog CMOS circuit design for low-power and high-speed VLSI
Semiconductor device physics and scaling
Preferred qualifications
Design and Automation Engineers
Knowledge of semiconductor device physics, process scaling, and advanced technology nodes.
Experience with industry standard CAD tools for schematic entry, circuit simulation, custom layout, and design/layout verification, from vendors such as Cadence, Synopsys, and Siemens.
Development of PCells or PyCells
Algorithmic development
EDA Physical Verification tools: ICV, Calibre, PVS
Antenna, Fill insertion
RC extraction tools: StarRC, Quantus,
MOSFETs model
Foundry experience / Process Design Kit (PDK)
Development of PCells or PyCells
Software Engineers
Proficient with UNIX/Linux computing platform
Software development/programming in Ruby, Perl, Java, C++, TCL, Lisp, Scheme.
Artificial Intelligence, Machine Learning (AI/ML)
Experience with web technologies, DevOps tools.
Experience with CAD tools from Cadence, (Virtuoso, Spectre and its scripting language SKILL), Synopsys (Custom Designer, Hspice, Star-RC, IC Validator) and Mentor (Calibre)
Semiconductor, SoC/IP Physical design
Knowledge of semiconductor device physics, process scaling, and advanced technology nodes.
Industry standard CAD tools for schematic entry, circuit simulation, custom layout, and design/layout verification, from vendors such as Cadence, Synopsys, and Siemens.
Design Compiler (DC), IC Compiler (ICC2), Fusion Compiler (FC), Genus, or Innovus
Layout verification using ICV/Calibre.
Pre-silicon or post-silicon validation/verification
PCells or PyCells development
Floorplan optimization for block Power
Logic Synthesis, Place & Route, Static Timing
Timing budgeting and analysis
Power grid design and IR analysis
Intel
Phoenix Arizona
United States
Information Technology
(No Timezone Provided)
Job Description
Have you taken a career break and had your resume rejected because of your resume gap? Intel is offering 16-week paid returnships for experienced professionals ready to return to the workforce. If you have taken a break of at least one year for the following reasons we welcome you to apply:
Starting or raising a family
Military service/military spouse
Community service/volunteer work
Caring for a family member
Teaching
Now is an exciting time for Intel’s Design Enablement Group! This position is within the Design Enablement (DE) organization of Technology Development (TD). At Intel, Design Enablement is one of the key pillars enabling Intel to deliver winning products in the marketplace. Your work will directly enable design teams to get to market faster with leadership products on cutting edge technologies and partner with Technology Development to deliver cost-effective, competitive design platform.
In this position you will help us with the following responsibilities:
Develop, design, and test analog, high-speed I/O, and memory circuits in Intel’s leading-edge technology nodes and optimize power/performance/area (PPA) to provide feedback that drives design-technology co-optimization for Intel process technologies.
Work with suppliers of CAD tools for custom design, layout, and design signoff to enable and validate features supporting the requirements of leading-edge process technologies.
Develop and validate technology files and other collaterals used by industry standard custom design, layout, and signoff CAD tools, including PCells/PyCells.
Develop automation software and scripts for generation and validation of Process Design Kit (PDK) collaterals and analysis of CAD tool results.
Develop automation to generate schematics, layouts, and library collaterals.
Develop and evaluate analog / mixed signal components for use with test equipment and other hardware systems.
Conduct or participate in multidisciplinary research and collaborate with design, layout and/or hardware engineers in the design, development, and utilization of productivity enhancement layout tools and design rule checkers, electronic data processing systems software.
Determines computer user needs, advises hardware designers on machine characteristics that affect software systems such as storage capacity, processing speed, and input/output requirements, designs and develops compilers and assemblers, utility programs, and operating systems.
Work closely with runset developers and rule writers on validating the rules.
Work with EDA on tool developments/improvements to enhance performance, add functionality and improve capacity.
Validate Process Design Kit (PDK)
Working with multiple EDA companies to co-develop extraction solutions that will be used both internally and as part of Intel's foundry program.
Analyzing and testing programs and products before formal launch
Troubleshooting coding problems quickly and efficiently to ensure a productive workplace
Software Engineer
In this position you will help us with one or more of the following responsibilities:
Behavioral traits that we are looking for:
Written and verbal communication skills
Teamwork, problem-solving, and data analysis
Ability to work across geographical locations
These positions are not eligible for Immigration Sponsorship.
These roles can be done remotely.
Qualifications
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications
Candidates must have been out of the paid workforce for at least one year.
You should have Bachelor’s degree OR Master's degree OR PhD in Electrical Engineering, Computer Engineering, Computer Science, or other related Electrical Scientific STEM field, with 3+ years of work experience in one or more of the following areas:
Design of CMOS analog/mixed-signal, custom digital, memories, data converters, RF, or high-speed circuits.
Layout of analog, RF, or digital circuits on advanced process technology nodes.
Programming or scripting in Python, Perl, Tcl, SKILL, C++, or Unix shell.
Circuit design: VLSL, circuit simulation
Design automation: ASIC Design, Place and Route, Virtuoso
Physical design: cadence virtuoso, layout automation, physical verification, parasitics, runsets
Semiconductor physics, devices modeling
Electromagnetic simulation
Programming languages: python/skill/Perl/ruby
Solving problems using efficient computer algorithm and programming techniques.
Software development/programming in Python languages
Object oriented programming, data structures, algorithms, and database.
Solving problems using efficient computer algorithm and programming techniques.
Software development/programming in Python languages
Object oriented programming, data structures, algorithms, and database.
Circuit design and VLSI technology
Computer architecture, RTL, Verilog, System Verilog, exposure to OVM UVM
Knowledge of Chip floor planning, layout integration, layout design rules and schematic/layout comparison debug and validation
Experience with floor planning, layout design, and verification CAD tools
Digital system RTL based design, including DFT, system architecture, and integration of various IPs into subsystems
Digital, mixed-signal, memory, and/or analog CMOS circuit design for low-power and high-speed VLSI
Semiconductor device physics and scaling
Preferred qualifications
Design and Automation Engineers
Knowledge of semiconductor device physics, process scaling, and advanced technology nodes.
Experience with industry standard CAD tools for schematic entry, circuit simulation, custom layout, and design/layout verification, from vendors such as Cadence, Synopsys, and Siemens.
Development of PCells or PyCells
Algorithmic development
EDA Physical Verification tools: ICV, Calibre, PVS
Antenna, Fill insertion
RC extraction tools: StarRC, Quantus,
MOSFETs model
Foundry experience / Process Design Kit (PDK)
Development of PCells or PyCells
Software Engineers
Proficient with UNIX/Linux computing platform
Software development/programming in Ruby, Perl, Java, C++, TCL, Lisp, Scheme.
Artificial Intelligence, Machine Learning (AI/ML)
Experience with web technologies, DevOps tools.
Experience with CAD tools from Cadence, (Virtuoso, Spectre and its scripting language SKILL), Synopsys (Custom Designer, Hspice, Star-RC, IC Validator) and Mentor (Calibre)
Semiconductor, SoC/IP Physical design
Knowledge of semiconductor device physics, process scaling, and advanced technology nodes.
Industry standard CAD tools for schematic entry, circuit simulation, custom layout, and design/layout verification, from vendors such as Cadence, Synopsys, and Siemens.
Design Compiler (DC), IC Compiler (ICC2), Fusion Compiler (FC), Genus, or Innovus
Layout verification using ICV/Calibre.
Pre-silicon or post-silicon validation/verification
PCells or PyCells development
Floorplan optimization for block Power
Logic Synthesis, Place & Route, Static Timing
Timing budgeting and analysis
Power grid design and IR analysis