Senior Design Verification Engineer - Customer Liaison (100% remote)

Encore Semi, Inc.

San Jose California

United States

Engineering
(No Timezone Provided)

Position Title: Senior Design Verification Engineer - Customer Liaison
Location: 100% remote
Full-time: Salary + Benefits + Bonuses

As Senior Design Verification Engineer and customer liaison you will have the following responsibilities:
• Run and debug existing block level tests (SystemVerilog, C, Assembly Language, other) in an internal restricted environment that are already passing in our full internal environment
• Make improvements to the verification environment
• Automate verification runs using scripts
• Coverage closure, add and hit functional coverage goals for new features
• Assist an external customer with replicating tests in their environment
• Act as a liaison between customer and internal experts when the customer needs debug assistance beyond the candidates experience
• Assist with customer IP verification (UVM based)

Requirements: 
• Excellent communication skills
• Experience with functional Design Verification of logic blocks within an ASIC or SoC
• Experience setting up and improving verification infrastructure, writing tests and driving functional coverage and debugging failures
• Strong experience with SystemVerilog for Verification as well as experience with UVM
• Strong debugging experience
• Knowledge of C/C++, Python, Makefiles, Perl, Ruby, Assembly Language
• 7+ years of experience as a Design Verification Engineer

Senior Design Verification Engineer - Customer Liaison (100% remote)

Encore Semi, Inc.

San Jose California

United States

Engineering

(No Timezone Provided)

Position Title: Senior Design Verification Engineer - Customer Liaison
Location: 100% remote
Full-time: Salary + Benefits + Bonuses

As Senior Design Verification Engineer and customer liaison you will have the following responsibilities:
• Run and debug existing block level tests (SystemVerilog, C, Assembly Language, other) in an internal restricted environment that are already passing in our full internal environment
• Make improvements to the verification environment
• Automate verification runs using scripts
• Coverage closure, add and hit functional coverage goals for new features
• Assist an external customer with replicating tests in their environment
• Act as a liaison between customer and internal experts when the customer needs debug assistance beyond the candidates experience
• Assist with customer IP verification (UVM based)

Requirements: 
• Excellent communication skills
• Experience with functional Design Verification of logic blocks within an ASIC or SoC
• Experience setting up and improving verification infrastructure, writing tests and driving functional coverage and debugging failures
• Strong experience with SystemVerilog for Verification as well as experience with UVM
• Strong debugging experience
• Knowledge of C/C++, Python, Makefiles, Perl, Ruby, Assembly Language
• 7+ years of experience as a Design Verification Engineer